1. Field of the Invention
The present invention relates to a semiconductor device formed on a silicon-on-insulator (SOI) substrate.
2. Description of the Related Art
Metal-insulator-semiconductor field effect transistors (MISFETs), typically metal-oxide-semiconductor field effect transistors (MOSFETs) such as p-channel MOSFETs (pMOS devices) and n-channel MOSFETs (nMOS devices), derive several advantages from being formed on an SOI substrate instead of a bulk silicon substrate. One advantage is that there are no pn junctions at the bottoms of the source and drain regions of the transistors, so the transistors have less parasitic capacitance and operate faster. Another advantage is that mutually adjacent devices are completely isolated from each other, so no parasitic elements are formed and malfunctions such as latch-up do not occur.
The devices formed on an SOI substrate are classified as partially depleted or fully depleted. Both types include a semiconductor layer formed on an insulating layer, but a fully depleted device has a thinner semiconductor layer, so that when turned on, it becomes substantially free of carriers of one type (holes, for an nMOS device). Fully depleted SOI devices are particularly fast because, as there is no depletion layer capacitance, a channel forms quickly when a voltage is applied to the gate (the device has a sharp sub-threshold characteristic). The thinness of the semiconductor layer and the presence of the insulating layer also suppress short-channel effects.
SOI devices are not without problems, however. Since the body of each device is electrically isolated, excess carriers of the depleted type (holes, in an nMOS device) generated by impact ionization in the drain vicinity cannot escape from the channel region. This so-called substrate floating effect lowers the threshold voltage of the device and reduces its source-drain breakdown voltage. In analog circuits the substrate floating effect is particularly problematic because it kinks the voltage-current operating characteristic of the device and produces large changes in current in response to certain small voltage changes. Suppressing the substrate floating effect is a key issue in devices that must withstand high source-drain voltages or operate with linear characteristics.
A known method of suppressing the substrate floating effect is to implant germanium into the highly doped source and drain areas exterior to the gate sidewalls. Germanium has a narrower band gap than silicon, so the presence of germanium in the source region lowers the source-channel potential barrier, enabling excess electrons (in a pMOS device) or holes (in an nMOS device) that accumulate in the channel region to escape from the device through its source electrode. Japanese Patent Application Publication (JP) No. 10-12883 describes a pMOS device of this type (e.g., in paragraphs 0019-0023 and FIGS. 1 and 2). JP 4-313242 describes an nMOS device of this type (e.g., in paragraphs 0008-0011 and FIG. 1).
Fabrication of devices of this type, however, requires an additional germanium ion implantation process, which makes it necessary to install costly additional fabrication equipment and modify the layout of the fabrication line. A further problem is that the formation of a silicon-germanium drain layer lowers the potential barrier on the drain side as well as the source side, leading to increased leakage of current between the source and drain.
Another way to suppress the substrate floating effect is to replace part of the pn junction between the source and channel regions with a Schottky junction. As described in JP 2000-269503 (e.g., in paragraphs 0023-0031 and FIGS. 1 and 3), this is done by forming a mesa of photoresist on part of the isolation region that surrounds the device, and then forming the highly doped source and drain regions by slanted implantation of an impurity from four directions, followed by metal silicide formation. A small part of the source region, shadowed by the resist mask and the gate electrode during three of the four implantations, is shallower than the silicidation depth and is replaced entirely with silicide material, creating a Schottky junction through which excess carriers can escape.
A problem with this method is that the width of the pn junction between the source and channel regions is reduced, so the device must be widened in order to obtain an adequate current driving capability. Another problem is that the Schottky junction is formed at only one end of the device and cannot provide adequate removal of accumulated carriers from the entire channel region if the device is very wide. Providing Schottky junctions at fixed intervals along the width of the device would pose difficult fabrication problems and would greatly increase the size of the device.
It would be desirable to have a way to suppress the substrate floating effect without requiring enlargement of the device or implantation of germanium.